We are looking for a Physical Design Lead to join our team

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
10 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
Experience with Electronic design automation (EDA) tools (i.e. Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk).

15 years of experience in the domain of static timing analysis.
Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Knowledge of semiconductor device physics and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full-chip static timing topics, including clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.

Own chip timing constraint creation and validation, timing sign-off margins and checklist criteria. Perform full chip timing analysis and timing Engineering Change Order (ECO) creation, and oversee final timing sign-off for complex Application-specific integrated circuits (ASIC).
Lead both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
Perform technical evaluations of Electronic design automation (EDA) tools and provide recommendations, documentation, and training.
Debug flow issues reported by your wider team and work with EDA vendors to resolve them where necessary.

Physical Design Lead, Static Timing Analysis