We are looking for a Design Engineer to join our team
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with RTL coding using Verilog/SystemVerilog.
- 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
Preferred qualifications:
- Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with low-power design techniques such as clock gating, power gating, and DVFS.
- Experience with SOC implementation standards, interfaces (i.e. AXI) and scripting languages (i.e. Tcl, Python or Perl).
- Experience in UPF for low-power design, including power intent specification, verification, and implementation.
- Experience with formal verification methods and design for testability (DFT) techniques.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
Responsibilities
- Contribute to the development and successful delivery of complex silicon systems. Design and implement RTL code for various digital blocks, including complex control logic, and on-chip data paths.
- Develop and maintain Unified Power Format (UPF) specifications for power management of the design, including power domain definitions, power state transitions, and isolation strategies.
- Take ownership of power signoff using industry standard tools coordinating deliverables from block owners.
- Collaborate with verification and physical design engineers to ensure the functionality and power integrity of the design.
- Contribute to the development and improvement of design flows, tools and methodologies.
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